Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment

In this article we present a structured approach to formal hardware verification bymodeling circuits at the register-transfer level using a restricted form of higher-order logic. Thisrestricted form of higher-order logic is sufficient for obtaining succinct descriptions of hierarchicallydesigned register-transfer circuits. By exploiting the structure of the underlying hardware proofs andlimiting the form of descriptions used, we have attained nearly complete automation in proving theequivalences of the specifications and implementations. A hardware-specific tool called MEPHISTOconverts the original goal into a set of simpler subgoals, which are then automatically solved by ageneral-purpose, first-order prover called FAUST. Furthermore, the complete verification frameworkis being integrated within a commercial VLSI CAD framework.